1. Field of the Invention
The present invention relates to power on reset circuits, and more particularly, to a power on reset circuit that is incorporated in a semiconductor device and generates a reset signal for resetting the semiconductor device at the time of power on.
2. Description of the Background Art
Conventionally, a semiconductor integrated circuit device (for example, DRAM, SRAM) is provided with a power on reset circuit (hereinafter, referred to as a xe2x80x9cPOR circuitxe2x80x9d) for resetting an internal circuit when an external power supply voltage VDD is turned on.
An output signal POR# of POR circuit remains at an L level until external power supply voltage VDD is raised from 0 V to a prescribed voltage Vres. When external power supply voltage VDD exceeds Vres, output signal POR# attains an H level. Voltage Vres is set lower than a certain range of the power supply voltage with which a product is guaranteed to normally operate. Herein, such a range is called a xe2x80x9cguaranteed rangexe2x80x9d. For example, if a product is designed to operate with 3.3 V (hereinafter, such product is referred to as a xe2x80x9c3.3 V productxe2x80x9d), the guaranteed range of the power supply voltage is normally from 3.0 V to 3.6 V. Thus, Vres is set approximately at 2.5 V in this case. During a time period in which power supply voltage VDD is not greater than Vres and signal POR# is at an L level, the internal circuitry of the semiconductor integrated circuit device, or more specifically, a redundant circuit of a memory device, a register or state machine of every kind, is initialized.
In the semiconductor integrated circuit device, in association with miniaturization of MOS transistors, the power supply voltage has been downscaled from initial 5 V to 3.3 V or to 2.5 V, further to 1.8 V or to 1.5 V. Consequently, Vres of POR circuit has also been downscaled.
FIG. 9 is a circuit diagram showing a configuration of such POR circuit 30, which is similar to the one disclosed in U.S. Pat. No. 5,703,510.
Referring to FIG. 9, POR circuit 30 includes a P channel MOS transistor 31, an N channel MOS transistor 32, capacitors 33, 34, and CMOS inverters 35-37. P channel MOS transistor 31 is connected between a line of power supply potential VDD and a node N1, and has its gate connected to node N1. P channel MOS transistor 31 constitutes a diode element. N channel MOS transistor 32 is connected between node N1 and a line of ground potential GND, and has its gate connected to a line of power supply potential VDD. N channel MOS transistor 32 constitutes a resistance element of high resistance. Capacitor 33 is connected between node N1 and a line of ground potential GND.
Inverter 35 includes a P channel MOS transistor 38 and an N channel MOS transistor 39. P channel MOS transistor 38 is connected between a line of power supply potential VDD and a node N2, and has its gate connected to node N1. N channel MOS transistor 39 is connected between node N2 and a line of ground potential GND, and has its gate connected to node N1.
Inverter 36 includes a P channel MOS transistor 40 and an N channel MOS transistor 41. P channel MOS transistor 40 is connected between a line of power supply potential VDD and node N1, and its gate is connected to node N2. N channel MOS transistor 41 is connected between node N1 and a line of ground potential GND, and its gate is connected to node N2. Inverters 35 and 36 constitute a latch circuit.
Capacitor 34 is connected between a line of power supply potential VDD and node N2. Node N2 is connected to an input node of inverter 37. An output signal of inverter 37 becomes signal POR#.
Hereinafter, Vres of POR circuit 30 will be described. In this POR circuit 30, to obtain Vres lower than that would be obtained by the POR circuit disclosed in the above-mentioned U.S. Pat. No. 5,703,510, the diode element (P channel MOS transistor 31) connected between the line of power supply potential VDD and node N1 is reduced from the two stages to one stage, and at the same time, the threshold voltage VTC of inverter 35 is reduced to the level of the threshold voltage VTN of N channel MOS transistor 39.
More specifically, threshold voltage VTC of CMOS inverter 35 is expressed as follows:                     VTC        =                  xe2x80x83                ⁢                              VDD            +            VTP            +                          VTN              ⁢                                                B                  R                                                                          1            +                                          B                R                                                                            =                  xe2x80x83                ⁢                                                            VDD                +                VTP                                                              B                  R                                                      +            VTN                                              1                                                B                  R                                                      +            1                              
wherein VTP is a threshold voltage of P channel MOS transistor 38; xcex2R represents a ratio xcex2N/xcex2P between xcex2N of N channel MOS transistor 39 and xcex2P of P channel MOS transistor 38. xcex2N represents a ratio WN/LN of a gate width WN to a gate length LN of N channel MOS transistor 39, and xcex2P represents a ratio WP/LP of a gate width WP to a gate length LP of P channel MOS transistor 38. Thus, by adjusting xcex2N=WN/LN and xcex2P=WP/LP, it is possible to make xcex2R=xcex2N/xcex2P larger than 1, whereby VTC nearly equal to VTN is attained.
If node N1 is at an L level, P channel MOS transistor 40 of inverter 36 is rendered non-conductive, and N channel MOS transistor 41 is conductive. If xcex2N of N channel MOS transistor 41 is made sufficiently small, potential V1 of node N1 becomes approximately equal to VDDxe2x88x92VTP, wherein VTP represents a threshold voltage of P channel MOS transistor 40.
If potential V1 of node N1 exceeds threshold potential VTN of inverter 35, potential V1 of node N1 inverts from an L level to an H level. Thus, power supply voltage VDD at the time when potential V1 of node N1 rises from an L level to an H level, i.e., Vres, becomes equal to VTN+VTP.
FIG. 10 shows time charts illustrating the operation of POR circuit 30 shown in FIG. 9. Referring to FIG. 10, at the initial state, node N1 is at a ground potential GND since it is grounded through a resistance element (N channel MOS transistor 32) of high resistance. Assume that external power supply potential VDD is switched on at time t0 and power supply potential VDD rises towards 1.8 V in proportion to time. When potential VDD greater than VTP, the diode element (N channel MOS transistor 31) turns on, and potential V1 of node N1 becomes equal to VDDxe2x88x92VTP.
At time t1, when potential V1 (=VDDxe2x88x92VTP) of node N1 exceeds threshold potential VTN of inverter 35, the output level of inverter 35 inverts from an H level to an L level, and the output level of inverter 36 rises from an L level to an H level, so that potential V1 of node N1 rises from VDDxe2x88x92VTP to VDD. Power supply voltage VDD at this time is Vres, and Vres=VTN+VTP in this POR circuit 30. Therefore, signal POR# is at an L level from time t0 to time t1, and it rises to an H level at time t1. Even if power supply voltage VDD fluctuates in a range higher than VTN afterwards, V1=VDD, and thus, signal POR# remains at the H level (time t1-t7). When power supply voltage VDD drops lower than VTN (time t8), MOS transistors 31, 38, 39, 40, 41 are rendered non-conductive. Electric charges stored in capacitor 33 are discharged through the resistance element (N channel MOS transistor 32) of high resistance, and POR circuit 30 returns to its initial state.
When power supply voltage VDD of a semiconductor integrate circuit device is downscaled, the threshold voltage of a MOS transistor should be reduced correspondingly. In practice, however, to lower power consumption by restricting a leakage current, the threshold voltage of MOS transistor is not downscaled. More specifically, the threshold voltage of MOS transistor, which was 0.8 V for 5 V and 3 V products, is maintained at 0.8 V even for 1.8 V and 1.5 V products. Thus, Vres of the POR circuit 30 shown in FIG. 9 becomes equal to VTN+VTP=0.8+0.8=1.6 V.
The guaranteed range of the power supply voltage for a 1.8 V product is 1.62 V to 1.98 V. Thus, the margin guaranteed by Vres=1.6 V as above is not large enough. Further, POR circuit 30 of FIG. 9 cannot be used for a 1.5 V product.
Accordingly, an object of the present invention is to provide a power on reset circuit that can be used even in a low power consumption semiconductor device operative with low power supply voltage.
The power on reset circuit according to the present invention includes: an inverter that drives a reset signal to an activated level in response to reception of a power supply potential and a reference potential and drives the reset signal to an inactivated level in response to a potential of its input node exceeding a prescribed threshold potential; a first resistance element having one electrode receiving a power supply potential and the other electrode connected to the input node of the inverter; and a first transistor of a first conductivity type having its first electrode receiving a reference potential and its second electrode connected to the input node of the inverter, and rendered conductive in response to the reset signal attaining the activated level. Therefore, when power is turned on, a potential of the power supply voltage divided by a resistance value of the first resistance element and a conductive resistance value of the first transistor is supplied to the inverter, to drive the reset signal to the activated level. When the divided potential exceeds a threshold potential of the inverter, the reset signal is driven to the inactivated level. Thus, the level of the power supply voltage at which the reset signal is driven from the activated level to the inactivated level can be set lower than in the conventional case, so that even a semiconductor device consuming less power and operating with less power supply voltage is enabled to generate a reset signal.
Preferably, the first resistance element includes a second transistor of a second conductivity type having its first electrode receiving the power supply potential, its second electrode connected to the input node of the inverter, and its input electrode receiving the reference potential. In this case, the inverter receives a potential of the power supply voltage divided by the conductive resistance values of the first and second transistors.
Preferably, the inverter includes: a third transistor of the second conductivity type having its first electrode receiving the power supply potential, its second electrode connected to an output node of the inverter, and its input electrode connected to the input node of the inverter; and a fourth transistor of the first conductivity type having its first electrode receiving the reference potential, its second electrode connected to the output node, and its input electrode connected to the input node. The predetermined threshold potential is set approximately equal to a threshold potential of the fourth transistor. In this case, it is possible to set the threshold potential of the inverter to a lowest possible level.
Preferably, a first capacitor having one electrode receiving the reference potential and the other electrode connected to the input node of the inverter, and a second capacitor having one electrode receiving the power supply potential and the other electrode connected to the output node of the inverter are further provided. In this case, it is possible to stabilize the potentials of the input node and the output node of the inverter.
Still preferably, the first capacitor includes a fifth transistor of the first conductivity type having its first and second electrodes both receiving the reference potential and its input electrode connected to the input node of the inverter, and the second capacitor includes a sixth transistor of the second conductivity type having its first and second electrodes both receiving the power supply potential and its input electrode connected to the output node of the inverter. In this case, the first and second capacitors can readily be constituted.
Preferably, a seventh transistor of the first conductivity type having its first electrode and its input node receiving the reference potential and its second electrode connected to the input node of the inverter, and an eighth transistor of the second conductivity type having its first electrode and its input electrode both receiving the power supply potential and its second electrode connected to the output node of the inverter are further provided. In this case, it is possible to drive the reset signal to the activated level even if the power supply potential is slowly raised up, thereby preventing malfunction of the semiconductor device.
Preferably, a second resistance element having one electrode receiving the reference potential and the other electrode connected to the input node of the inverter is further provided. In this case, it is possible to discharge the charges in the input node of the inverter via the second resistance element to the line of the reference potential after stopping the application of the power supply potential, so that the input node of the inverter can be driven to the reference potential in a short period of time.
Still preferably, the second resistance element includes a ninth transistor of the first conductivity type having its first electrode receiving the reference potential, its second electrode connected to the input node of the inverter, and its input electrode receiving the power supply potential. In this case, it is readily possible to constitute the second resistance element.
Preferably, a tenth transistor of the first conductivity type having its first electrode receiving the power supply potential and its second electrode connected to the input node of the inverter, a third resistance element having one electrode receiving the power supply potential and the other electrode connected to the input electrode of the tenth transistor, and a third capacitor having one electrode receiving the reference potential and the other electrode connected to the input electrode of the tenth transistor are further provided. In this case, after stopping the application of the power supply potential, charges at the input node of the inverter can be discharged via the first transistor, so that the input node of the inverter can be driven to the reference potential in a short period of time.
Still preferably, the third resistance element includes an eleventh transistor of the second conductivity type having its first electrode receiving the power supply potential, its second electrode connected to the input node of the inverter, and its input electrode receiving the reference potential. In this case, the third resistance element can readily be constituted.
Preferably, a fourth resistance element connected in series with the first resistance element between a line of the power supply potential and the input node of the inverter and having a resistance value that is sufficiently larger than the conductive resistance value of the first resistance element, and a fifth resistance element connected in series with the first transistor between a line of the reference potential and the input node of the inverter and having a resistance value sufficiently larger than the conductive resistance value of the first transistor are further provided. In this case, a potential of the power supply voltage divided by the fourth and fifth resistance elements is applied to the inverter, so that it is possible to stabilize the threshold voltage of the power on reset circuit.
Still preferably, the fourth and fifth resistance elements are made of the same material to have the same width, and have their resistance values set by their respective lengths. In this case, it is possible to suppress the variation in the resistance values of the fourth and fifth resistance elements. Thus, the threshold voltage of the power on reset circuit can further be stabilized.
Still preferably, the fourth and fifth resistance elements are each formed of a diffusion resistance layer. In this case, it is readily possible to constitute the fourth and fifth resistance elements.
Still preferably, the fourth and fifth resistance elements are each formed of a polycrystalline silicon layer. In this case, again, the fourth and fifth resistance elements can be readily constituted.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.